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天 Oğuz Meteer 天 @[email protected]

@BitlogIT

Digital ASIC designer | PhD candidate @UTwente | Writer at the BitLog technology blog | #FPGA and #ASIC connoisseur | Twitch: https://t.co/MUib6EPK3s

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Pinned

I'm doing an ASIC roundup of open source #riscv cores. Here is the SERV @risc_v v1.10 by @OlofKindgren synthesized and P&R'd using a 65 nm standard cell library. Max. freq: 1408 MHz Die area: 0.029584 mm2 1/x

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天 Oğuz Meteer 天 @[email protected] Reposted

Introducing a SKY130 ROM compiler project I've been working on for a while. youtu.be/MlqDm_Kg0u8 This is just a quick intro to the project with following episodes diving into all the tech details of the design.


天 Oğuz Meteer 天 @[email protected] Reposted

A small step for a hobby logic designer, but a giant leap for @tinytapeout The first official RISC-V uLinux ASIC, yes, ASIC, you heard that right, is operational and functional. Just dabbling in chip design as a hobbyist. Haha, what an awesome achievement! Thanx to @matthewvenn


天 Oğuz Meteer 天 @[email protected] Reposted

🚨Amnesia Generation. The Internet will lose over 500,000 books. The Internet Archive has been ordered to delete them. The Internet Archive is appealing and essential for libraries to lend, preserve ensure access to out-of-print books. Sign a protest: change.org/p/let-readers-…


天 Oğuz Meteer 天 @[email protected] Reposted

i just need a few more cosmic rays to hit my bank

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